This application claims the priority of Korean Patent Application No. 2004-0017162, filed on Mar. 13, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a linear circuit simulation method, and more particularly, to a power distribution network simulation method using a variable reduction method.
2. Description of the Related Art
There have been proposed many simulation methods to analyze a power distribution network of a linear circuit, particularly, a semiconductor integrated circuit. One of the conventional methods is disclosed in US Patent Laid-open No. US2002/0199160 A1. The conventional method has a limitation in simulating a large circuit including tens of millions of nodes and resisters. However, it is difficult to overcome the limitation.
Recently, IBM and Motorola have proposed a multi-grid method and a hierarchical method, respectively. However, both of the methods still have a problem in that there are errors beyond allowable tolerance when both of the methods are applied to a large circuit including tens of millions of nodes and resistors.